丁香蜜桃综合cb_国产在线精品国自产拍愿_中文亚洲少妇自拍_欧美日韩二级片_极品人妻大胆尝试50p_黑人性做爰视频播放_国产欧美日韩精品系列_亚洲视频一区在线观看

1 Topology and placement of DDR3 memory chips
DDR3 chips should put at the suitable place for fly-by topology layout and close to the
controller chips.
2 Trace routing guide – Clock

Route the CLK/CLK# signals as a differential pair. Use 5/5/5mil to control the
differential impedance to 100ohm.

Route the CLK/CLK# pair as “Fly-by” type to make the traces symmetrical.

Place the CLK/CLK# termination at the end of Fly-by type connect point.

The two branches of Fly-by topology should be controlled as balance as
possible and the mismatch should be less than 5ps.
3 Trace routing guide --DQS/DQSN/DQ/DQM
DQS, DQSN,
DQ & DQM

The delay mismatch of intra groups should be less than 5 ps.

The delay mismatch of inter groups should be less than 15 ps.

The same group should have equal numbers and either “NO” or “two” via
DQS/DQSN
Rout the DQS/DQSN as differential pair(5/5/5) and as short as possible
DQ/DQM
Rout the DQ/DQM traces in 5mil wide and as short as possible.
4 Trace routing guide --Command/Address
 Route the CMD&ADDR signals in 5mil width to control impedance.
 Route the CMD&ADDR signals as similar “Fly-by” topology to make the trace
symmetrical.
 The termination resistor should be placed ½” to 1” beyond the primary split in a
tee configuration or beyond the final DRAM in a daisy chain configuration.
100ohm pull up and pull down.
 Route serpentine traces to control the CMD&ADDR group mismatch within
70ps.(include substrate delay data)
 To control data crosstalk, the gap between traces should be at least 15mil
 Each via delay is 10.5ps for the 2-layer stack up board.
3 / 5
5 Layout guide --Power/GND Plane and decoupling cap
For power, ground and decoupling capacitors, several issues need special attention
during the placement and layout. To make power of both SOC and memory chips stable,
many capacitors need be placed under the SOC and memory chips. Capacitors should
be included 10uF, 0.1uF and 0.01uF to lower the noises of various band of frequency.
The location of decoupling capacitors for several power and ground balls need be as
near to the balls as possible.
The ground is used as a signal return path for DDR trace line. As the stack of the
2 layer board, the each signal should have a 5 mil ground line close to it. And make
sure the GND connection is solid enough. And add some via one the memory ground
line connect the top and bottom ground.
6 Trace routing guide –MVREF

Add 0.1uF decoupling cap at every VREF Pin as near as possible.

Make the VREF trace as wide as possible and at least 10mil.

Use precise divider resistors (1%) to make sure the VREF voltage is stable.
7 Flash Memory Interface
Since the flash memory speed is higher and higher, we need to take more care
about flash interface layout. It is better to make the traces as short as possible and
make sure they have the great possible complete reference plane on GND and VCC
layer. So we do not suggest to layout flash trace on PCB inner layer for 2-layer PCB.
8 HDMI Interface
Differential pair of signals
 The High Definition Multimedia Interface (HDMI) video signals should be
transmitted on high speed differential pairs.
 To get continued impedance and control differential impedance within
100ohm+-15%, integrated reference plane must be provided.
 Differential pair routing rule---5/5/5/5/5mil GND/line/air gap/line/GND
with recommended stack up to get 100ohm differential impedance.
HDMI ESD/EMI Protection
 HDMI receivers must have ESD protection components.
 Common mode choke always be added to have better EMI result
 Recommend SEMTECH’s ESD suppresser RClamp0524 ,Parasitical
capacitance < 0.3Pf
4 / 5
9 LVDS/VBO/IDP interface
 Make sure LVDS trace as short as possible
 Make sure LVDS trace differential impedance about 100 ohms.
 If needed, add common mode choke to improve LVDS bus EMI/ESD
performance.
 Differential pair routing rule---5/5/5mil
with recommended stack up to get 100ohm differential impedance
 The air gap between LVDS differential pairs should more than 25mil
10 USB interface
Differential Pair Signals
 Make sure USB differential pair as short as possible
 Make sure USB trace differential impedance is about 90 ohm
 Differential pair routing rule---5/6/5/6/5mil
with recommended stack up to get 90ohm differential impedance
 Supply integrated reference plane for differential pair to have continue impedance
 In order to minimize effect of crosstalk, signal traces should have at least 25mil
air gap to other signals.
ESD
 ESD protection parts should be added near the USB connector
 CM1214-02MS is used for ESD protection in Fusion EP board.
 To make differential impedance meet USB specification, special routing around
CM1214-02MS should be implemented to compensate the differential impedance
skew brought by these parts, refer to layout file for details.
11 Analog Video input
 Analog inputs should stay away from digital signal and be at least 8mil width.
 INN nets capacitors should be placed near to chip as closer as possible.
 ESD protection parts should be added at analog input connectors.
 PC input should add 100ohm resistor as filter to make RGB input has better
phase.
 The power of analog block should be as cleaner as possible. It is better to
separate analog power from digital power with ferrate beads or inductors.
5 / 5
12 Ethernet interface
 Route RX(TX) +/- as differential pair, using 5/5/5/5/5 4/6/4 rule to control the
differential impedance to 100ohm.
 PHY should close to UXL chip if it is possible.
 Separate RJ45 connector’s ground from system ground
 Make sure Inner Layer copper being kept away under transformer area to
avoid the noise from LAN bus.
13 Tuner IF signal

Route IF differential input on the top layer, shield with GND and make it as
short as possible.